Design and Analysis of Low Standby Leakage Current and Reduce Ground Bounce Noise of Static CMOS 10T Full Adder

In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic operation like addition, multiplication and computational model. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also address generation in processor and microcontroller memories which are employed in large scale system at higher speed .In this paper, we have proposed a modified 10T full adder based on PTL using multi-threshold CMOS technique. Here we use forward body biased multimode (MTCMOS) technique to evaluate standby leakage current, power and ground bounce noise. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltage and temperatures. The forward body biased (FBB) multimode MTCMOS technique has been implemented on conventional 10T full adder circuit with 45 nm technology parameters for simulations. By using this technique the standby leakage current reduction can be improved by 90 % and leakage power to 30 % as compared to base 10T full adder. Ground bounce noise can be reduced to 55 % as compared to the conventional adder. KeywordsGround bounce noise, Leakage power, Multi-threshold CMOS, Full adder, Pass transistor logic, Sleep transistor. African Journal of Computing & ICT Reference Format: R. Singh & S. Akashe (2014). Design and Analysis of Low Standby Leakage Current and Reduce Ground Bounce Noise of Static CMOS 10T Full Adder. Afr J. of Comp & ICTs. Vol 7, No. 2. Pp 143-150.